1. Field of the Invention
The invention relates generally to an electronic circuit for dynamic phase alignment and, more particularly, to a self-adjusting circuit which can be used to achieve phase alignment in coincident pulse edges between two clocks with the same frequency, when one of the clocks is derived from a frequency-multiplied version of the other.
2. Description of the Related Art
In a digital computer system, there may be many subsystems or components that operate at different clock speeds. For example, a central processing unit (CPU) may operate at 500 MHz, whereas a memory unit may operate at 100 MHz. This is true for systems created with discrete components as well as for those created as a highly integrated ASIC system-on-chip (SOC) which contains many different subsystems in a single ASIC chip.
A common scheme for clocking subsystems is to use a low speed reference clock and a phase-locked loop (PLL) to create one or more higher-frequency multiplied primary clock(s). While PLLs generally ensure phase alignment between such primary clocks, they cannot guarantee phase alignment in other clocks which are derived from the primary clocks by an external clock generation logic circuit. Phase alignment between a reference clock and a derived clock is required to allow synchronous interface between them.
Two common methods for achieving phase alignment between clocks include a) a one-time handshake between clock domains and b) a scheme of using the derived clock as feedback to a PLL. Each of these methods can impose limitations on maximum frequency, minimum frequency, and/or permitted clocking ratios.
Accordingly, there exists a need for accurate phase alignment of different clocks in a computer system. In addition, there is a need for a reliable phase alignment technique that can be implemented easily and also is capable of dealing with very high speed clock circuits.
The present invention provides an inexpensive, reliable solution to phase alignment problems that face many system designers and other engineers. The invention includes a dynamic phase alignment circuit comprising a delay circuit connected to a derived clock tree, a detecting circuit portion connected to the delay circuit and to a reference clock tree, and a correcting circuit portion connected to the detecting circuit portion and to a clock generator.
In another aspect of the invention, the phase of the derived clock is dynamically aligned by delaying the derived clock, detecting the phase difference between the delayed clock and the reference clock, and correcting the phase of the delayed clock by incrementally realigning the phase of the delayed clock until alignment is achieved.
The present invention has numerous advantages over other phase alignment schemes. For example, the dynamic phase alignment circuit of the present invention requires only a minimal number of logic gates to implement, thereby minimizing additional cost of implementing this invention.
Moreover, the present invention presents a phase alignment solution that satisfies the stringent timing requirements of clock generation logic without requiring strict timing challenges. The dynamic phase alignment circuit of the present invention will allow a CPU clock as fast as 500 MHz or faster to be used with reference clocks that are typically 33 or 66 MHz.
Additionally, the present invention has the advantage of being able to recover alignment automatically and without additional logic circuits, even if a derived clock is stopped and then restarted during normal operation. Such a stoppage could occur during power management operations that would stop clocks to minimize power.